With the advent of nanometer technologies, circuit performance constraints are becoming ever more stringent. In this context, automated timing analysis and optimization becomes imperative for the design of high-performance circuits that must satisfy a demanding set of constraints. Timing overviews the state of the art in timing analysis and optimization, and is intended to serve as a compendium that can provide an introduction to the uninitiated reader, as a ready reference for a practitioner, or as a source for the accomplished researcher. A comprehensive overview of the basics of timing analysis is provided, and this is augmented with techniques that incorporate physical effects arising in deep submicron and nanometer technologies. The book provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels. The intended audience includes CAD tool developers, graduate students, research professionals, and the merely curious.

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zlib/Engineering/S. Sapatnekar/Timing_674865.pdf

Sapatnekar, Sachin

Springer US

United States, United States of America

Boston, MA, United States, 2004

Boston, Massachusetts, 2004

1 edition, June 2, 2004

2004, PS, 2004

2004, 2007

lg247074

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Includes bibliographical references (p. [259]-290) and index

Cover......Page 1
Contents......Page 8
Acknowledgements......Page 12
1. PREDUCTION/INTROFACE......Page 14
2.1 Introduction......Page 18
2.2 Formulation of circuit equations......Page 19
2.3 Examples of equation formulation by inspection......Page 26
2.4 Solution of nonlinear equations......Page 27
2.5 Solution of differential equations......Page 31
2.6 Putting it all together......Page 37
2.7 A primer on solving systems of linear equations......Page 38
2.8 Summary......Page 44
3.1 Introduction......Page 46
3.2 Interconnect modeling......Page 49
3.3 Typical interconnect structures......Page 51
3.4 The Elmore delay metric......Page 53
3.5 Asymptotic waveform evaluation......Page 57
3.6 Krylov subspace-based methods......Page 68
3.7 Fast delay metrics......Page 76
3.8 Realizable circuit reduction......Page 81
3.9 Summary......Page 83
4.1 Introduction......Page 84
4.2 Identifying a logic stage......Page 85
4.3 Delay calculation under purely capacitive loads......Page 86
4.4 Effective capacitance: Delays under RC loads......Page 90
4.5 Capacitive coupling effects......Page 98
4.6 Summary......Page 109
5.2 Representation of combinational and sequential circuits......Page 110
5.3 False paths......Page 120
5.4 Finding the k most critical paths......Page 122
5.5 Summary......Page 124
6.1 Introduction......Page 126
6.2 Modeling parameter variations......Page 129
6.3 Early work on statistical STA......Page 134
6.4 Statistical STA in the absence of spatial correlation......Page 136
6.5 Statistical STA under spatial correlations......Page 139
6.6 Summary......Page 145
7.1 Introduction......Page 146
7.2 Clocking disciplines: Edge-triggered circuits......Page 148
7.3 Clocking disciplines: Level-clocked circuits......Page 150
7.4 Clock schedule optimization for level-clocked circuits......Page 157
7.5 Timing analysis of domino logic......Page 158
7.6 Summary......Page 162
8.1 Introduction......Page 164
8.2 Transistor sizing......Page 165
8.3 The TILOS algorithm......Page 170
8.4 Transistor sizing using convex programming......Page 174
8.5 Lagrangian multiplier approaches......Page 175
8.6 Timing budget based optimization......Page 179
8.7 Generalized posynomial delay models for transistor sizing......Page 180
8.8 Dual V[sub(t)] optimization......Page 188
8.9 Resolving short path violations......Page 190
8.10 Summary......Page 191
9.1 Accidental and deliberate clock skew......Page 194
9.2 Clock network construction......Page 196
9.3 Clock skew optimization......Page 203
9.4 Clock skew optimization with transistor sizing......Page 209
9.5 Timing analysis of sequential circuits for skew scheduling......Page 214
9.6 Wave pipelining issues......Page 216
9.7 Deliberate skews for peak current reduction......Page 217
9.8 Summary......Page 218
10.1 Introduction to retiming......Page 220
10.2 A broad overview of research on retiming......Page 224
10.3 Modeling and assumptions for retiming......Page 227
10.4 Minimum period optimization of edge-triggered circuits......Page 229
10.5 Minimum area retiming of edge-triggered circuits......Page 240
10.6 Minimum period retiming of level-clocked circuits......Page 253
10.8 Summary......Page 260
11. CONCLUSION......Page 262
A.1 Cubic equations......Page 264
A.2 Quartic equations......Page 265
B–A Gaussian approximation of the PDF of the maximum of two Gaussians......Page 266
C.1 Proof of convexity......Page 268
C.2 Relation of a generalized posynomial program to a posynomial program......Page 270
References......Page 272
D......Page 304
P......Page 305
T......Page 306
Z......Page 307

Statistical timing analysis is an area of growing importance in nanometer te- nologies‚ as the uncertainties associated with process and environmental var- tions increase‚ and this chapter has captured some of the major efforts in this area. This remains a very active field of research‚ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits‚ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book‚ the reader is referred to [LNPS00‚ HN01‚ JH01‚ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.
Erscheinungsdatum: 02.06.2004

"This book provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels." "The intended audience includes CAD tool developers, graduate students, research professionals, and the merely curious."--BOOK JACKET.

2010-05-17