This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
Erscheinungsdatum: 18.02.2010

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zlib/Computers/Hardware/Toby Doorn, Roelof Salters (auth.), José Monteiro, René van Leuken (eds.)/Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers_1267438.pdf

Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The ... (Lecture Notes in Computer Science, 5953)

PATMOS 2009 (2009 Delft, Netherlands)

José Monteiro; ‎Rene van Leuken

PATMOS (Workshop)

Spektrum Akademischer Verlag. in Springer-Verlag GmbH

Springer Berlin Heidelberg : Imprint: Springer

Steinkopff. in Springer-Verlag GmbH

Springer London, Limited

Springer Nature

Lecture notes in computer science -- 5953, LNCS sublibrary: SL 1-theoretical computer science and general issues, Berlin, New York, Germany, 2010

Lecture Notes in Computer Science, Online-ausg, Berlin, Heidelberg, 2010

LNCS sublibrary, 5953, 1st ed. 2010, Berlin, Heidelberg, 2010

Lecture notes in computer science, 5953, Berlin, cop. 2010

Springer Nature, Berlin, Heidelberg, 2010

Germany, Germany

1, 20100206

lg1134556

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Includes bibliographical references and index.
Also issued online.

Front Matter....Pages -
Robust Low Power Embedded SRAM Design: From System to Memory Cell....Pages 1-1
Variability in Advanced Nanometer Technologies: Challenges and Solutions....Pages 2-2
Subthreshold Circuit Design for Ultra-Low-Power Applications....Pages 3-3
SystemC AMS Extensions: New Language – New Methods – New Applications....Pages 4-4
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation....Pages 5-15
Interpreting SSTA Results with Correlation....Pages 16-25
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units....Pages 26-35
Exponent Monte Carlo for Quick Statistical Circuit Simulation....Pages 36-45
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis....Pages 46-55
A Hardware Implementation of the User-Centric Display Energy Management....Pages 56-65
On-chip Thermal Modeling Based on SPICE Simulation....Pages 66-75
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures....Pages 76-85
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip....Pages 86-95
Data-Driven Clock Gating for Digital Filters....Pages 96-105
Power Management and Its Impact on Power Supply Noise....Pages 106-115
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems....Pages 116-126
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique....Pages 127-135
Crosstalk in High-Performance Asynchronous Designs....Pages 136-145
Modeling and Reducing EMI in GALS and Synchronous Systems....Pages 146-155
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop....Pages 156-164
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms....Pages 165-174
Dynamic Data Type Optimization and Memory Assignment Methodologies....Pages 175-185
Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation....Pages 186-195
Write Invalidation Analysis in Chip Multiprocessors....Pages 196-205
Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform....Pages 206-215
BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation....Pages 216-226
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering....Pages 227-236
Low Energy Voltage Dithering in Dual V DD Circuits....Pages 237-246
Product On-Chip Process Compensation for Low Power and Yield Enhancement....Pages 247-255
Low-Power Soft Error Hardened Latch....Pages 256-265
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities....Pages 266-275
Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation....Pages 276-285
The Magic Rule of Tiles: Virtual Delay Insensitivity....Pages 286-296
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates....Pages 297-306
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)....Pages 307-316
Routing Resistance Influence in Loading Effect on Leakage Analysis....Pages 317-325
Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks....Pages 326-335
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process....Pages 336-346
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding....Pages 347-356
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder....Pages 357-366
Back Matter....Pages -

Welcome To The Proceedings Of The 19th International Workshop On Power And Timingmodeling, Optimizationandsimulation, Patmos2009.overtheyears, Patmoshasevolvedintoanimportanteuropeanevent, Whereresearchersfrom Both Industry And Academia Discuss And Investigate The Emerging Challenges In Future And Contemporary Applications, Design Methodologies, And Tools Required For The Development Of The Upcoming Generations Of Integrated Circuits And S- Tems. Patmos 2009 Was Organized By Tu Delft, The Netherlands, With Sp- Sorship By The Nirict Design Lab And Cadence Design Systems, And Technical Co-sponsorshipbytheieee.furtherinformationabouttheworkshopisavailable Athttp: //ens.ewi.tudelft.nl/patmos09. The Technical Programof Patmos 2009 Contained State-of-the-arttechnical Contributions, Three Invited Keynotes, And A Special Session On Systemc-ams Extensions. The Technical Program Focused On Timing, Performance, And Power Consumption, As Well As Architectural Aspects With Particular Emphasis On M- Eling, Design, Characterization, Analysis, And Optimization In The Nanometer Era. The Technical Program Committee, With The Assistance Of Additional Expert Reviewers, Selected The 36 Papers Presented At Patmos. The Papers Were - Ganized Into 7 Oral Sessions (with A Total Of 26 Papers) And 2 Poster Sessions (with A Total Of 10 Papers). As Is Customary For The Patmos Workshops, Full Papers Were Required For Review, And A Minimum Of Three Reviews Were Received Per Manuscript.

Annotation This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies

2012-03-17