This Volume Contains The Proceedings Of The 12th International Conference On Computer Aided Veri?cation (cav 2000) Held In Chicago, Illinois, Usa During 15-19 July 2000. The Cav Conferences Are Devoted To The Advancement Of The Theory And Practice Of Formal Methods For Hardware And Software Veri?cation. The Con- Rence Covers The Spectrum From Theoretical Foundations To Concrete Applications, With An Emphasis On Veri?cation Algorithms, Methods, And Tools Together With Techniques For Their Implementation. The Conference Has Traditionally Drawn Contributions From Both Researchers And Practitioners In Academia And Industry. This Year 91 Regular Research Papers Were Submitted Out Of Which 35 Were - Cepted, While 14 Brief Tool Papers Were Submitted, Out Of Which 9 Were Accepted For Presentation. Cav Included Two Invited Talks And A Panel Discussion. Cav Also Included A Tutorial Day With Two Invited Tutorials. Many Industrial Companies Have Shown A Serious Interest In Cav, Ranging From Using The Presented Technologies In Their Business To Developing And M- Keting Their Own Formal Veri?cation Tools. We Are Very Proud Of The Support We Receive From Industry. Cav 2000 Was Sponsored By A Number Of Generous Andforward-lookingcompaniesandorganizationsincluding:cadencedesign- Stems, Ibm Research, Intel, Lucent Technologies, Mentor Graphics, The Minerva Center For Veri?cation Of Reactive Systems, Siemens, And Synopsys. Thecavconferencewasfoundedbyitssteeringcommittee:edmundclarke (cmu), Bob Kurshan (bell Labs), Amir Pnueli (weizmann), And Joseph Sifakis (verimag). Invited Talks And Tutorials -- Keynote Address: Abstraction, Composition, Symmetry, And A Little Deduction: The Remedies To State Explosion -- Invited Address: Applying Formal Methods To Cryptographic Protocol Analysis -- Invited Tutorial: Boolean Satisfiability Algorithms And Applications In Electronic Design Automation -- Invited Tutorial: Verification Of Infinite-state And Parameterized Systems -- Regular Papers -- An Abstraction Algorithm For The Verification Of Generalized C-slow Designs -- Achieving Scalability In Parallel Reachability Analysis Of Very Large Circuits -- An Automata-theoretic Approach To Reasoning About Infinite-state Systems -- Automatic Verification Of Parameterized Cache Coherence Protocols -- Binary Reachability Analysis Of Discrete Pushdown Timed Automata -- Boolean Satisfiability With Transitivity Constraints -- Bounded Model Construction For Monadic Second-order Logics -- Building Circuits From Relations --^ Combining Decision Diagrams And Sat Procedures For Efficient Symbolic Model Checking -- On The Completeness Of Compositional Reasoning -- Counterexample-guided Abstraction Refinement -- Decision Procedures For Inductive Boolean Functions Based On Alternating Automata -- Detecting Errors Before Reaching Them -- A Discrete Strategy Improvement Algorithm For Solving Parity Games -- Distributing Timed Model Checking — How The Search Order Matters -- Efficient Algorithms For Model Checking Pushdown Systems -- Efficient Büchi Automata From Ltl Formulae -- Efficient Detection Of Global Properties In Distributed Systems Using Partial-order Methods -- Efficient Reachability Analysis Of Hierarchical Reactive Machines -- Formal Verification Of Vliw Microprocessors With Speculative Execution -- Induction In Compositional Model Checking -- Liveness And Acceleration In Parameterized Verification -- Mechanical Verification Of An Ideal Incremental Abr Conformance Algorithm --^ Model Checking Continuous-time Markov Chains By Transient Analysis -- Model-checking For Hybrid Systems By Quotienting And Constraints Solving -- Prioritized Traversal: Efficient Reachability Analysis For Verification And Falsification -- Regular Model Checking -- Symbolic Techniques For Parametric Reasoning About Counter And Clock Systems -- Syntactic Program Transformations For Automatic Abstraction -- Temporal-logic Queries -- Are Timed Automata Updatable? -- Tuning Sat Checkers For Bounded Model Checking -- Unfoldings Of Unbounded Petri Nets -- Verification Diagrams Revisited: Disjunctive Invariants For Easy Verification -- Verifying Advanced Microarchitectures That Support Speculation And Exceptions -- Tool Papers -- Focs – Automatic Generation Of Simulation Checkers From Formal Specifications -- If: A Validation Environment For Timed Asynchronous Systems -- Integrating Ws1s With Pvs -- Pet: An Interactive Software Testing Tool -- A Proof-carrying Code Architecture For Java --^ The Statemate Verification Environment -- Taps: A First-order Verifier For Cryptographic Protocols -- Vinas-p: A Tool For Trace Theoretic Verification Of Timed Asynchronous Circuits -- Xmc: A Logic-programming-based Verification toolset. E. Allen Emerson, A. Prasad Sistla (eds.) Includes Bibliographical References And Index.

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Computer aided verification : 12. international conference, CAV 2000 : Chicago, IL, USA, July 15-19, 2000 : proceedings ( E. Allen Emerson, A. Prasad Sistla (eds.)

International conference on computer aided verification

E. Allen Emerson ; A. Prasad Sistla,Springer

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CAV (Conference)

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Springer Berlin Heidelberg : Imprint : Springer

Springer Spektrum. in Springer-Verlag GmbH

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Springer London, Limited

Springer Nature

Lecture notes in computer science, 1855, 1st ed. 2000, Berlin, Heidelberg, 2000

Springer Nature, Berlin, Heidelberg, 2006

1 edition, August 17, 2000

Berlin [etc, c2000

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Front Matter....Pages -
Keynote Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion....Pages 1-1
Invited Address: Applying Formal Methods to Cryptographic Protocol Analysis....Pages 2-2
Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation....Pages 3-3
Invited Tutorial: Verification of Infinite-state and Parameterized Systems....Pages 4-4
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs....Pages 5-19
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits....Pages 20-35
An Automata-Theoretic Approach to Reasoning about Infinite-State Systems....Pages 36-52
Automatic Verification of Parameterized Cache Coherence Protocols....Pages 53-68
Binary Reachability Analysis of Discrete Pushdown Timed Automata....Pages 69-84
Boolean Satisfiability with Transitivity Constraints....Pages 85-98
Bounded Model Construction for Monadic Second-Order Logics....Pages 99-112
Building Circuits from Relations....Pages 113-123
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking....Pages 124-138
On the Completeness of Compositional Reasoning....Pages 139-153
Counterexample-Guided Abstraction Refinement....Pages 154-169
Decision Procedures for Inductive Boolean Functions Based on Alternating Automata....Pages 170-185
Detecting Errors Before Reaching Them....Pages 186-201
A Discrete Strategy Improvement Algorithm for Solving Parity Games....Pages 202-215
Distributing Timed Model Checking — How the Search Order Matters....Pages 216-231
Efficient Algorithms for Model Checking Pushdown Systems....Pages 232-247
Efficient Büchi Automata from LTL Formulae....Pages 248-263
Efficient Detection of Global Properties in Distributed Systems Using Partial-Order Methods....Pages 264-279
Efficient Reachability Analysis of Hierarchical Reactive Machines....Pages 280-295
Formal Verification of VLIW Microprocessors with Speculative Execution....Pages 296-311
Induction in Compositional Model Checking....Pages 312-327
Liveness and Acceleration in Parameterized Verification....Pages 328-343
Mechanical Verification of an Ideal Incremental ABR Conformance Algorithm....Pages 344-357
Model Checking Continuous-Time Markov Chains by Transient Analysis....Pages 358-372
Model-Checking for Hybrid Systems by Quotienting and Constraints Solving....Pages 373-388
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification....Pages 389-402
Regular Model Checking....Pages 403-418
Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems....Pages 419-434
Syntactic Program Transformations for Automatic Abstraction....Pages 435-449
Temporal-logic Queries....Pages 450-463
Are Timed Automata Updatable?....Pages 464-479
Tuning SAT Checkers for Bounded Model Checking....Pages 480-494
Unfoldings of Unbounded Petri Nets....Pages 495-507
Verification Diagrams Revisited: Disjunctive Invariants for Easy Verification....Pages 508-520
Verifying Advanced Microarchitectures that Support Speculation and Exceptions....Pages 521-537
FoCs – Automatic Generation of Simulation Checkers from Formal Specifications....Pages 538-542
IF: A Validation Environment for Timed Asynchronous Systems....Pages 543-547
Integrating WS1S with PVS....Pages 548-551
PET: An Interactive Software Testing Tool....Pages 552-556
A Proof-Carrying Code Architecture for Java....Pages 557-560
The Statemate Verification Environment....Pages 561-567
TAPS: A First-Order Verifier for Cryptographic Protocols....Pages 568-571
VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits....Pages 572-575
XMC: A Logic-Programming-Based Verification Toolset....Pages 576-580
Back Matter....Pages -

Computer Aided Verification: 12th International Conference, CAV 2000, Chicago, IL, USA, July 15-19, 2000. Proceedings
Author: E. Allen Emerson, Aravinda Prasad Sistla
Published by Springer Berlin Heidelberg
ISBN: 978-3-540-67770-3
DOI: 10.1007/10722167
Table of Contents:
Keynote Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion
Invited Address: Applying Formal Methods to Cryptographic Protocol Analysis
Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation
Invited Tutorial: Verification of Infinite-state and Parameterized Systems
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits
An Automata-Theoretic Approach to Reasoning about Infinite-State Systems
Automatic Verification of Parameterized Cache Coherence Protocols
Binary Reachability Analysis of Discrete Pushdown Timed Automata
Boolean Satisfiability with Transitivity Constraints
Bounded Model Construction for Monadic Second-Order Logics
Building Circuits from Relations
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
On the Completeness of Compositional Reasoning
Counterexample-Guided Abstraction Refinement
Decision Procedures for Inductive Boolean Functions Based on Alternating Automata
Detecting Errors Before Reaching Them
A Discrete Strategy Improvement Algorithm for Solving Parity Games
Distributing Timed Model Checking — How the Search Order Matters
Efficient Algorithms for Model Checking Pushdown Systems

This volume contains the proceedings of the 12th International Conference on Computer Aided Veri?cation (CAV 2000) held in Chicago, Illinois, USA during 15-19 July 2000. The CAV conferences are devoted to the advancement of the theory and practice of formal methods for hardware and software veri?cation. The con- rence covers the spectrum from theoretical foundations to concrete applications, with an emphasis on veri?cation algorithms, methods, and tools together with techniques for their implementation. The conference has traditionally drawn contributions from both researchers and practitioners in academia and industry. This year 91 regular research papers were submitted out of which 35 were - cepted, while 14 brief tool papers were submitted, out of which 9 were accepted for presentation. CAV included two invited talks and a panel discussion. CAV also included a tutorial day with two invited tutorials. Many industrial companies have shown a serious interest in CAV, ranging from usingthe presented technologies in their business to developing and m- keting their own formal veri?cation tools. We are very proud of the support we receive from industry. CAV 2000 was sponsored by a number of generous andforward-lookingcompaniesandorganizationsincluding:CadenceDesign- stems, IBM Research, Intel, Lucent Technologies, Mentor Graphics, the Minerva Center for Veri?cation of Reactive Systems, Siemens, and Synopsys. TheCAVconferencewasfoundedbyitsSteeringCommittee:EdmundClarke (CMU), Bob Kurshan (Bell Labs), Amir Pnueli (Weizmann), and Joseph Sifakis (Verimag).
Erscheinungsdatum: 28.06.2000

Appendix: Selected Definitions and Proofs 288
Introduction 306
Background 307
VLIW Architecture Verified 309
Discussion 311
Exploiting Conservative Approximations 312
Decomposing the Computation of the Correctness Criterion 315
Modeling Multicycle Functional Units and Branch Prediction 317
Experimental Results 318
Conclusions 320
Introduction 354
Introduction 399
Related Work 401
Improved Reachability Search 402
Invariant Verification 403
Fast Frontier Splitting 404
On-the-Fly Verification 406
Prioritized Traversal 406
Experimental Results 407
Comparing Splitting Algorithms 408
Capacity Improvement 410
Conclusions 410
References 412

Annotation This book constitutes the refereed proceedings of the 12th International Conference on Computer Aided Verification, CAV 2000, held in Chicago, IL, U.S.A. in July 2000. The 35 revised full papers presented together with 9 tool papers were carefully reviewed & selected from 91 submissions. The papers address all current aspects of the theory & practice of formal methods for hardware & software verification. Emphasis is given to verification algorithms, methods, & tools & their implementation

This book constitutes the refereed proceedings of the 12th International Conference on Computer Aided Verification, CAV 2000, held in Chicago, IL, USA in July 2000. The 35 revised full papers presented together with 9 tool papers were carefully reviewed and selected from 91 submissions. The papers address all current aspects of the theory and practice of formal methods for hardware and software verification. Emphasis is given to verification algorithms, methods, and tools and their implementation

This book constitutes the proceedings of the 26th International Conference on Computer Aided Verification, CAV 2014, held as part of the Vienna Summer of Logic, VSL 2014, in Vienna, Austria, in July 2014.

2013-08-01