The Biannual Formal Methods In Computer Aided Design Conference (fmcad 2000)is The Third In A Series Of Conferences Under That Title Devoted To The Use Of Discrete Mathematical Methods For The Analysis Of Computer Hardware And So- Ware. The Work Reported In This Book Describes The Use Of Modeling Languages And Their Associated Automated Analysis Tools To Specify And Verify Computing Systems. Functional Veric Ation Has Become One Of The Principal Costs In A Modern Computer Design E Ort. In Addition,verica Tion Of Circuit Models, Timing,power, Etc., Requires Even More Eo Rt. Fmcad Provides A Venue For Academic And - Dustrial Researchers And Practitioners To Share Their Ideas And Experiences Of Using Discrete Mathematical Modeling And Veric Ation. It Is Noted With Interest By The Conference Chairmen How This Area Has Grown From Just A Few People 15 Years Ago To A Vibrant Area Of Research, Development, And Deployment. It Is Clear That These Methods Are Helping Reduce The Cost Of Designing Computing Systems. As An Example Of This Potential Cost Reduction, We Have Invited David Russino Of Advanced Micro Devices, Inc. To Describe His Veric Ation Of ?oating-point - Gorithms Being Used In Amd Microprocessors. The Program Includes 30 Regular Presentations Selected From 63 Submitted Papers. Applications Of Hierarchical Verification In Model Checking -- Applications Of Hierarchical Verification In Model Checking -- Invited Talk -- Trends In Computing -- Invited Paper -- A Case Study In Formal Verification Of Register-transfer Logic With Acl2: The Floating Point Adder Of The Amd Athlon Tm Processor -- Contributed Papers -- An Algorithm For Strongly Connected Component Analysis In N Log N Symbolic Steps -- Automated Refinement Checking For Asynchronous Processes -- Border-block Triangular Form And Conjunction Schedule In Image Computation -- B2m: A Semantic Based Tool For Blif Hardware Descriptions -- Checking Safety Properties Using Induction And A Sat-solver -- Combining Stream-based And State-based Verification Techniques -- A Comparative Study Of Symbolic Algorithms For The Computation Of Fair Cycles -- Correctness Of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification In Esl --^ Formal Verification Of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology For The Formal Analysis Of Asynchronous Micropipelines -- A Methodology For Large-scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions And A Case Study -- Modeling And Parameters Synthesis For An Air Trafficmanagement System -- Monitor-based Formal Specification Of Pci -- Sat-based Image Computation With Application In Reachability Analysis -- Sat-based Verification Without State Space Traversal -- Scalable Distributed On-the-fly Symbolic Model Checking -- The Semantics Of Verilog Using Transition System Combinators -- Sequential Equivalence Checking By Symbolic Simulation -- Speeding Up Image Computation By Using Rtl Information -- Symbolic Checking Of Signal-transition Consistency For Verifying High-level Designs -- Symbolic Simulation With Approximate Values --^ A Theory Of Consistency For Modular Synchronous Systems -- Verifying Transaction Ordering Properties In Unbounded Bus Networks Through Combined Deductive/algorithmic Methods -- Visualizing System Factorizations With Behavior Tables. Warren A. Hunt, Jr., Steven D. Johnson, Eds. Includes Bibliographical References And Index.

lgrsnf/Cs_Computer science/CsLn_Lecture notes/F/Formal Methods in Computer-Aided Design, 3 conf., FMCAD 2000(LNCS1954, Springer, 2000)(ISBN 3540412190)(573s)_CsLn_.pdf

nexusstc/Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings/9c85f1f900c22ee65988500f77add748.pdf

zlib/Computers/Computer Science/Robert Beers, Rajnish Ghughal, Mark Aagaard (auth.), Warren A. Hunt Jr., Steven D. Johnson (eds.)/Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings_765446.pdf

Formal methods in computer-aided design: third international conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000: proceedings

Warren A Hunt; Steven D Johnson; International Conference on Formal Methods in Computer-Aided Design, FMCAD

Warren A. Jr Hunt; Steven D Johnson; SpringerLink (Online service)

FMCAD 2000 (2000 Austin, Tex.)

Springer Berlin Heidelberg : Imprint: Springer

Springer Spektrum. in Springer-Verlag GmbH

Steinkopff. in Springer-Verlag GmbH

Springer London, Limited

SpringerLink [host

Springer Nature

Lecture notes in computer science -- 1954., New York, New York State, 2000

Lecture notes in computer science, 1st ed. 2000, Berlin, Heidelberg, 2000

Lecture notes in computer science, 1954, Berlin ; New York, 2000

Lecture notes in computer science, Berlin [etc, 2000

1 edition, November 27, 2000

Germany, Germany

1, 20071129

Kolxo3

lg339861

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Includes index.

Applications of Hierarchical Verification in Model Checking....Pages 1-19
Trends in Computing....Pages 20-21
A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor....Pages 22-55
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps....Pages 56-73
Automated Refinement Checking for Asynchronous Processes....Pages 74-91
Border-Block Triangular Form and Conjunction Schedule in Image Computation....Pages 92-109
B2M: A Semantic Based Tool for BLIF Hardware Descriptions....Pages 110-126
Checking Safety Properties Using Induction and a SAT-Solver....Pages 127-144
Combining Stream-Based and State-Based Verification Techniques....Pages 145-161
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles....Pages 162-179
Correctness of Pipelined Machines....Pages 181-198
Do You Trust Your Model Checker?....Pages 199-216
Executable Protocol Specification in ESL....Pages 217-236
Formal Verification of Floating Point Trigonometric Functions....Pages 254-270
Hardware Modeling Using Function Encapsulation....Pages 271-282
A Methodology for the Formal Analysis of Asynchronous Micropipelines....Pages 283-299
A Methodology for Large-Scale Hardware Verification....Pages 300-319
Model Checking Synchronous Timing Diagrams....Pages 320-335
Model Reductions and a Case Study....Pages 336-352
Modeling and Parameters Synthesis for an Air TrafficManagement System....Pages 353-371
Monitor-Based Formal Specification of PCI....Pages 372-390
SAT-Based Image Computation with Application in Reachability Analysis....Pages 391-408
SAT-Based Verification without State Space Traversal....Pages 409-426
Scalable Distributed On-the-Fly Symbolic Model Checking....Pages 427-441
The Semantics of Verilog Using Transition System Combinators....Pages 442-459
Sequential Equivalence Checking by Symbolic Simulation....Pages 460-479
Speeding Up Image Computation by Using RTL Information....Pages 480-491
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs....Pages 492-506
Symbolic Simulation with Approximate Values....Pages 507-522
A Theory of Consistency for Modular Synchronous Systems....Pages 523-541
Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods....Pages 542-556
Visualizing System Factorizations with Behavior Tables....Pages 557-574

Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings
Author: Warren A. Hunt Jr., Steven D. Johnson
Published by Springer Berlin Heidelberg
ISBN: 978-3-540-41219-9
DOI: 10.1007/3-540-40922-X
Table of Contents:
Applications of Hierarchical Verification in Model Checking
Trends in Computing
A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Automated Refinement Checking for Asynchronous Processes
Border-Block Triangular Form and Conjunction Schedule in Image Computation
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
Checking Safety Properties Using Induction and a SAT-Solver
Combining Stream-Based and State-Based Verification Techniques
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
Correctness of Pipelined Machines
Do You Trust Your Model Checker?
Executable Protocol Specification in ESL
Formal Verification of Floating Point Trigonometric Functions
Hardware Modeling Using Function Encapsulation
A Methodology for the Formal Analysis of Asynchronous Micropipelines
A Methodology for Large-Scale Hardware Verification
Model Checking Synchronous Timing Diagrams
Model Reductions and a Case Study
Modeling and Parameters Synthesis for an Air TrafficManagement System

The biannual Formal Methods in Computer Aided Design conference (FMCAD 2000)is the third in a series of conferences under that title devoted to the use of discrete mathematical methods for the analysis of computer hardware and so- ware. The work reported in this book describes the use of modeling languages and their associated automated analysis tools to specify and verify computing systems. Functional veric ation has become one of the principal costs in a modern computer design e ort. In addition,verica tion of circuit models, timing,power, etc., requires even more eo rt. FMCAD provides a venue for academic and - dustrial researchers and practitioners to share their ideas and experiences of using discrete mathematical modeling and veric ation. It is noted with interest by the conference chairmen how this area has grown from just a few people 15 years ago to a vibrant area of research, development, and deployment. It is clear that these methods are helping reduce the cost of designing computing systems. As an example of this potential cost reduction, we have invited David Russino of Advanced Micro Devices, Inc. to describe his veric ation of ?oating-point - gorithms being used in AMD microprocessors. The program includes 30 regular presentations selected from 63 submitted papers.
Erscheinungsdatum: 18.10.2000

The biannual Formal Methods in Computer Aided Design conference (FMCAD 2000)is the third in a series of conferences under that title devoted to the use of discrete mathematical methods for the analysis of computer hardware and so- ware. The work reported in this book describes the use of modeling languages and their associated automated analysis tools to specify and verify computing systems. Functional verification has become one of the principal costs in a modern computer design report. In addition,verification of circuit models, timing,power, etc., requires even more eo rt. FMCAD provides a venue for academic and industrial researchers and practitioners to share their ideas and experiences of using discrete mathematical modeling and verification. It is noted with interest by the conference chairmen how this area has grown from just a few people 15 years ago to a vibrant area of research, development, and deployment. It is clear that these methods are helping reduce the cost of designing computing systems. As an example of this potential cost reduction, we have invited David Russino of Advanced Micro Devices, Inc. to describe his verification of ?oating-point algorithms being used in AMD microprocessors. The program includes 30 regular presentations selected from 63 submitted papers

This book constitutes the refereed proceedings of the Third International Conference on Formal Methods in Computer-Aided Design, FMCAD 2000, held in Austin, Texas in November 2000. The 30 revised full papers presented together with two invited contributions were carefully reviewed and selected from 63 submissions. All current issues of research and development approaches based on formal methods for the design and analysis of systems are addressed. Among the topics covered are formal verification, formal specification, systems analysis, program analysis, model checking, automated modeling, program semantics, theorem proving, symbolic simulation, and transition systems

The formal hardware verification effort at AMD has emphasized theorem proving using ACL2 [3], and has focused on the elementary floating-point operations.

2011-01-08