This book covers the foundations of hardware/software codesign, on-chip communication, debugging, and verification, for heterogenous SoCs. Its primary objective is to empower designers in making informed decisions, guiding them to strike the perfect balance between flexibility and performance for their SoC designs. Readers will benefit from a detailed exploration of the essential elements of the hardware and software codesign framework, accompanied by a discussion of the driving motivations behind this approach. The author also provides an in-depth review of various hardware design architectures, shedding light on different design possibilities. Furthermore, the book presents key concepts concerning hardware and software communication, unraveling the intricate interactions within an SoC. This book provides a holistic introduction to the methodologies underpinning SoC design and verification, making it an indispensable companion for both novice and experienced designers navigating the ever-evolving landscape of hardware/software codesign.

lgrsnf/978-3-031-56152-8.epub

Springer Nature, Cham, 2024

Switzerland, Switzerland

1st ed. 2024, PS, 2024

Contents
1 An Introduction to Heterogeneous SoC Design and Verification “A Conceptual-Level”
1.1 Introduction
1.1.1 Introduction: Digital Design Flow
1.1.2 Introduction: Software
1.1.3 Introduction: How to Develop HW/SW Together?
1.1.4 Introduction: How to Run/Communicate HW/SW Together?
1.1.5 Introduction: SoC Case Studies
1.1.6 Introduction: IP Management
1.1.7 Conclusions
References
2 SoC Design Methodologies
2.1 Introduction: Hardware Design Methodologies
2.1.1 FPGA-Centric SoC Design
2.1.2 Processor-Centric SoC Design
2.1.3 HLS-Centric SoC Design
2.1.4 Data-Centric/Memory-Centric SoC Design
2.1.5 Hardware Accelerators-Centric SoC Design
2.1.6 ASIC-Based SoC Design
2.1.7 PCB-Based SoC Design
2.1.8 Application-Centric SoC Design
2.1.9 Conclusions
References
3 HW/SW Co-Exploration and Co-Design
3.1 HW/SW Partitioning
3.1.1 Design Space Exploration (DSE): HW/SW Co-Exploration Tradeoff
3.1.2 HW/SW Interfacing
3.1.3 Task Graph and Cost Function: Problem Definition
3.1.4 Petri Nets
3.1.5 UML Diagrams
3.1.6 Optimization Techniques for Manual HW/SW Partitioning: ML-Based Approach
3.2 HW/SW Communication
3.2.1 SCEMI
3.2.2 DPI-C
3.3 HW/SW Synchronization
3.3.1 Semaphore
3.3.2 Handshake
3.3.3 Bus Locking
3.3.4 Mutex
3.3.5 Interrupt
3.3.6 FIFO
3.4 HW/SW Co-Design Metrics
3.5 Conclusions
References
4 Pre-Silicon Verification and Post-Silicon Validation Methodologies
4.1 Introduction
4.2 Pre-Silicon Verification
4.2.1 Virtual Prototyping
4.2.2 FPGA Prototyping
4.2.3 Physical Prototyping
4.2.4 Emulation-Based Verification: Using FPGAs to Simulate ASICs
4.2.5 Simulation-Based Verification
4.2.6 Functional Verification
4.2.7 Directed-Testing Verification
4.2.8 Coverage-Driven Verification
4.2.9 UVM
4.2.10 Formal Verification
4.2.11 Verification IP Versus Design IP
4.2.12 Power-Aware Verification
4.2.13 Timing Verification
4.2.14 Safety Verification: Fault Simulation
4.2.15 Performance Verification: Meeting Bandwidth and Latency
4.2.16 Verification Challenges
4.2.17 How to Verify the Verification
4.2.18 Regression Testing Techniques
4.2.19 IP-XACT Methodology
4.2.20 Portable Stimulus Standard: Graph-Based Testing
4.3 Post-Silicon Validation
4.3.1 DFT Verification: Gate-Level Simulations
4.3.2 Physical Probing/Trace-Based Technique
4.3.3 Synthesizable Assertions for Post-Silicon Debug
4.4 Full-Chip SoC Verification: SoC Integration Testing
4.5 Data-Driven Verification: AI-Powered Verification
4.6 Conclusions
References
5 HW/SW Co-Verification and Co-Debugging
5.1 Co-Simulation
5.2 Co-Emulation
5.3 Co-Debugging
5.3.1 GDB: A GNU Debugger
5.3.2 Arm DS5 Debugger
5.3.3 MIPS SP55 Debugger
5.3.4 Lauterbach Trace32 Debugger
5.3.5 OpenOCD Debugger
5.3.6 Codelink
5.4 HW/SW Co-Verification Metrics
5.5 Conclusions
References
6 HW/SW Co-Optimization and Co-Protection
6.1 HW/SW Co-Optimization
6.1.1 Software Optimization
6.1.2 Hardware Optimization
6.1.3 HW/SW Compilation Time Optimization
6.1.4 HW Maximum Frequency Optimization
6.1.5 HW/SW Power Optimization
6.1.6 HW/SW Speed Optimization
6.1.7 HW Area Optimization
6.2 HW/SW Co-Protection
6.2.1 Hardware Oriented Security and Trust
6.3 Conclusions
References

2024-05-27