This book describes the state-of-the-art of technology and research on In-Memory Computing Hardware Accelerators for Data-Intensive Applications. The authors discuss how processing-centric computing has become insufficient to meet target requirements and how Memory-centric computing may be better suited for the needs of current applications. This reveals for readers how current and emerging memory technologies are causing a shift in the computing paradigm. The authors do deep-dive discussions on volatile and non-volatile memory technologies, covering their basic memory cell structures, operations, different computational memory designs and the challenges associated with them. Specific case studies and potential applications are provided along with their current status and commercial availability in the market.

lgli/Baker Mohammad-Yasmin Halawani (eds) In-Memory Computing Hardware Accelerators for Data-Intensive Applications (Springer 2024).pdf

lgrsnf/Baker Mohammad-Yasmin Halawani (eds) In-Memory Computing Hardware Accelerators for Data-Intensive Applications (Springer 2024).pdf

zlib/Computers/Hardware/Baker Mohammad, Yasmin Halawani/In-Memory Computing Hardware Accelerators for Data-Intensive Applications_26262024.pdf

Mohammad, Baker; Halawani, Yasmin

Springer Nature Switzerland AG

Springer Nature, Cham, 2023

Switzerland, Switzerland

producers:
Acrobat DC

Preface 5
Contents 7
Data-Centric Computing Paradigm Shift, and Domain-Specific Architecture and Hardware 8
1 Introduction 8
2 Data Centric, Computing Paradigm Shifts, Domain-Specific Designs 9
2.1 Latency 9
2.2 Security, and Privacy 10
2.3 Domain-Specific Architecture and Circuits 10
2.4 Low Quality Data 13
SRAM-Based In-Memory Computing: Circuits, Functions, and Applications 14
1 Introduction 14
2 Standard Memory Cell Design in SRAM 16
3 SRAM IMC/NMC Architectures and Designs 17
4 SRAM-IMC Based Search and Logic Operation 18
4.1 Search Operation 18
4.2 Boolean Logic AND, OR, NAND, NOR, XNOR, XOR, and IMC 23
5 Arithmetic Operations 27
5.1 Addition 27
5.2 Multiplication 29
5.3 SRAM Based Multiply-Accumulate Arithmetic Implementations 31
6 Potential Applications 34
6.1 CNNs Applications 35
6.2 Encryption Algorithms Application 36
6.3 Application for Machine Learning (ML) and Classification Algorithms 37
6.4 SRAM-IMC for CAM and Hamming Distance Computation 37
Proposed SRAM-IMC for Hamming Distance Computation 39
7 Challenges 39
7.1 Readout Precision vs. Signal Margin 40
7.2 Limitations of 6T SRAM 40
7.3 Process Variation 40
7.4 Read Disturb 42
7.5 Cell and Array Area 42
7.6 Multi-Bit Input Schemes for MAC Operations 42
8 Commercial Availability 43
In and Near-Memory Computing Using DRAM 45
1 Introduction 45
2 DRAM Organization 46
3 DRAM Access 48
4 DRAM Computing Architecture 50
4.1 Row Copy 51
4.2 Bulk Initialization 52
4.3 Bitwise Operation 53
5 Potential Applications 55
5.1 Accelerators for Machine Learning Using DRAM 55
5.2 IMC Using DRAM for Security Applications 57
True Random Number Generator (TRNG) 57
Physical Unclonable Function (PUF) 58
6 Challenges 61
7 Commercial Availability 61
MRAM-Based In-Memory Computing 62
1 Introduction 62
1.1 Chapter Organization 63
2 Overview 63
2.1 CMOS Integration 64
2.2 Basic Characteristics and Comparisons to Other Technologies 66
Speed 66
Power 66
Density 66
Data Retention and Endurance 66
3 Physics of Magnetic Tunnel Junctions 67
3.1 Critical Current Density 67
3.2 Dynamic Modeling 68
3.3 TMR 69
4 Chip Demonstrations and Commercialization 69
5 MRAM for In-Memory Computing 71
5.1 Possibilities and Challenges 72
5.2 Digital IMC 73
General-Purpose IMC 73
IMC for AI Applications 75
5.3 Analog IMC 76
STT-MRAM Crossbar Architectures 76
Neuromorphic MRAM-Based Systems 77
6 Case Study: A Mixed-Signal SNN Accelerator Using an STT Crossbar 78
6.1 2MTJ-2T Cell 80
6.2 Mapping SNN to the STT Crossbar 82
Noise Modeling 83
In-Memory Computing Using Phase Change Memory 85
1 Introduction 85
2 Operating Principle 86
2.1 Write Operation 86
2.2 Read Operation 86
2.3 Multi-Level Operation 87
3 Properties of PCM Devices 88
4 Potential Applications 89
4.1 Compressed Sensing and Recovery 89
4.2 Mixed-Precision IMC 91
4.3 Convolutional Neural Network (CNN) Inference 92
4.4 Spiking Neural Network (SNN) with PCM Synapses 93
4.5 Hyper-Dimensional Computing (HDC) 93
4.6 Similarity Search in Genomic Read Mapping 94
4.7 Case Study: PCM-Based IMC Array with Time-Domain Circuit for DNA Read Mapping 95
5 Challenges 97
6 Commercial Availability 99
Memristor-Based In-Memory Computing 101
1 Introduction 101
2 Operating Principles 102
2.1 Memristor Basics 102
2.2 Memristor Models 103
2.3 Memristor Crossbar 104
3 RRAM IMC Architecture and Designs 105
3.1 RRAM-Based Vector-Matrix Multiplication 105
3.2 RRAM-Based In-Memory Logic 107
3.3 RRAM-Based Neural Network Architectures 108
3.4 RRAM-Based Spiking Neural Network Architectures 109
3.5 RRAM-Based Hyperdimensional Computing 110
3.6 RRAM-Based Image Processing 110
3.7 RRAM-Based Image Compression 111
3.8 RRAM-Based Image Enhancement 111
4 Challenges 112
4.1 Device Level 112
Conductance Tuning Scheme 112
State Disturbance 113
Resistance Ratio 113
Symmetry of the Device 113
Crossbar Nanowire Resistance 113
4.2 Peripheral Circuit Level 114
Sneak Path Currents 114
Write/Access Latency 114
Optimizing Peripheral Circuitry 114
RESET Operation Before Every Write 115
4.3 System Level 115
Map Matrix Values to Memristor Conductance 115
Negative Value Representation Using Memristor Conductance 116
Mapping Algorithms and Hardware Training Schemes 117
5 Case Study: Transformer Attention Acceleration on Memristor 117
5.1 Performance Assessment and Discussion 121
6 Commercial Availability 123
In-Memory Computing Using FLASH Memory 126
1 Potential Applications 126
2 Challenges 127
3 Commercial Availability 127
Reference 129
Index 129

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Erscheinungsdatum: 26.09.2023

2023-09-26